chenbo

llvm ir have infinite logical register, so we need do register allocation at runtime? it's kind of crazy.

riscv: x0 ~ x31 llvm ir: x0 ~ x99999999... it's useful for compiler frontend implementation and backend optimization

> No, there must be at least 2 segments for the DMA engine to work correctly. Hi Alex. I wonder why there must be at least 2 segments for the...

Just make part3 required and reorder to 132. Part 3 is interesting too, and it is not so hard.

@fabianschuiki @fzi-hielscher Thank you for detailed explain the pros and the cons, and also very nice examples. It seems like more information will benefit future works. I will make effort...

also this code will wait in1 and in2 ``` module Test(output logic [31:0] out, input logic [31:0] in1, input logic [31:0] in2); always_comb begin out = in1; out = in2;...