Xu, Zefan

I have this problem, too. I think this is same as #30. I have done some test, which shows that this `input xxx` was matched to `Tags` or `entity.name.tag`...

Ok, I found the problem... If we write Verilog HDL code like ``` module asdf ( input some_input ); ``` Then `input some_input` will be matched to an `instantiation_patterns` in...

> 你好，我有一个问题，是不是香山的spec2006的测试需要跑在linux中？还是说，我可以不启动linux内核，直接跑spec2006的程序？ 请注意，您提出了一个新问题，请您新开一个 issue 提问。 Please note that you've raised a new question. Please open a new issue to ask it.

首先，请您按照 Issue 模板的指示完成提问前步骤。 First, Please follow issue template to finish steps before asking questions. 其次，请介绍更多细节，我们尚不清楚您在哪里添加的 `--prof-cfuncs`。 Second, please introduce more details. We still do not know where you add `--prof-cfuncs`....

At the moment, XiangShan does not support Q standard extension, specifically the Quad-Precision Floating-Point extension. I'm afraid that just modifying the Scala configuration won't allow you to obtain 128-bit modules....

请考虑使用更大的内存和更大的 swap 空间。`-Xmx` 参数的值也可以考虑继续增大。 Please consider using larger memory and increasing the swap space. You might also want to consider further increasing the value of the -Xmx parameter.

+1. When will this PR merged into master? 😣

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Please give more infomation of your workload. Also, please give the commit id of XiangShan that you used. By the way, have you tried to run your workload on NEMU?...

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