cbiker

leaving state in fsm if begin end not used in verilog

2

**Describe the bug** if code of case not use begin end in verilog state machine viewer can lost condition and transition to this state **To Reproduce** module pattern_generator_stm ( bla...

fsm isnt recognized - begin end bug

2

**Describe the bug** >>>I found that this problem is caused by code irregularities >>what is mean? code of example or code of teros? now i see that not only always...