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A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code

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Just found an issue on K230 when doing some auto-vectorization tests on https://github.com/UoB-HPC/TSVC_2. The vectorized `s1115` is like: ```asm .LBB9_7: # %vector.ph andi a6, s6, 256 vsetvli a2, zero, e32,...

I think we are in the same timezone? I received mine yesterday. Feel free to DM me on Fediverse (link in my profile) or `michael.crusoe`@`fu-berlin.de`

Hello: I am attempting to execute the bench on spike, and after running 'make all,' I encounter the following problem when attempting to execute the generated executable with spike: ```shell...

We are working on an open source multiple lane RVV for HPC market https://github.com/chipsalliance/t1 with intensive chaining support. To provide as much as possible memory bandwidth. We don’t support mmu...

- Widening reductions (`vfwredosum.vs`, `vfwredusum.vs`, `vwredsum.vs`, `vwredsumu.vs`) should allow LMUL=8 - `vrgatherei16.vv` should only disallow LMUL=8 for e8

Hi, I find your benchmark to be very valuable. Do you have any good ideas or suggestions for testing the performance (throughput or latency) of various vector load instructions? I...

Hi, I saw each RVV instruction throughput result here: https://camel-cdr.github.io/rvv-bench-results/bpi_f3/index.html If I want to test the execution throughput of each RVV instructions in other RISC-V board, could you give me...