Olaf Bernstein

@Anzooooo Great, I tried the PR, and the code here works now. I still run into other problems when I try to run my benchmark code, but I'll create a...

The last problem I mentioned was apparently caused by a nexus-am bug, almost all code from rvv-bench runs. The only things that don't include complex load store/stores, idl if those...

Looks like this is a problem again. I tried running the first example on the latest commit, and it freezes again in the DefaultConfig. Now any vector instruction seems to...

Idk why the CI works, I just tried with MinimalConfig again, and the above with just `vsetvli` fails an assertion: ``` Assertion failed at /xs-env/XiangShan/build/rtl/Rob.sv:37719. Core 0: ABORT at pc...

Ah, thanks. I thought nexus-am already does it, but apparently it just wasn't checked until NewCSR was merged. I'm rerunning the benchmarks now.

The first point should be fixed now, thanks. The current design just masks standalone LMUL and SEW, so I can't add `LMUL=8` `SEW!=8`, `vrgatherei16.vv` for now. I'll have to look...

The latest commit 7b3f7b6 fixes this, I'll update the results page soon. I've now updated the instruction cycle count measurement code to remove the destination vector dependency that processors without...

The table was also inspired by uops.info, but mine is way less sophisticated then that or yours. I was looking into adding RISC-V support to llvm-exegesis, which does something very...

Yeah, that sounds great. The current code works in freestanding mode with linux, porting it to other platforms only requires porting `exit()` and `memwrite()` in [nolibc.h](https://github.com/camel-cdr/rvv-bench/blob/main/nolibc.h). Memory allocation [is done](https://github.com/camel-cdr/rvv-bench/blob/main/bench/bench.h#L90)...

As far as I can tell this is a problem with spike or pk not exposing the `cycle` csr. I'm not sure whats going on though, as `pk` enables it...