Camel Coder
Camel Coder
I just realized that fixing this will be a bit more involved, as early versions of `verror_at` call `exit` internally, and I'm not sure if is UB: ```c static void...
Just to clarify the expected performance: * One call to the polar method generates two normal distributed numbers. * One call to the ratio method is approximately 80% faster but...
Isn't `choices.h` basically a library already? Separating it a bit more shouldn't be too hard. I'd be up to doing it, but I'm not sure in which direction @jhawthorn wants...
> Vector registers: RVV introduces 32-vector register files, each with a width of 128 bits or 256 bits That's not true, RVV vector registers can have any power of two...
Update I tried running it on a few other branches: adc944d tmp-backend-fixtiming-merge-master: same problem 824af1e vlsu-240315: same problem but worse, even a lower iteration count froze the simulation. I also...
I just tried running it on the development branches, and while it behaved the same on [fp-split](https://github.com/OpenXiangShan/XiangShan/tree/fp-split) and [new-csr](https://github.com/OpenXiangShan/XiangShan/tree/new-csr), the `mandelbrot` and `LUT4` code snippets completed successfully on the [vlsu-240315](https://github.com/OpenXiangShan/XiangShan/tree/vlsu-240315)...
I think the original implementation used a depth first search without the need of a hash table: http://kevingong.com/Polyominoes/ParallelPoly.html  The idea is to generate the objects using these inner/outer numbered...
I'm building a list of rvv benchmark results, which could be useful for this project, it currently has numbers for C906 and C910/C920: https://camel-cdr.github.io/rvv-bench-results/ A few performance notes on other...
Just dropping a few more reference here: neon2rvv: https://github.com/howjmay/neon2rvv if somebody plans to port vzip with rvv intrinsics: https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/289#issuecomment-1781385001
The risc-v summit talk about the rvv simde paper is online: https://www.youtube.com/watch?v=puvnghbIAV4