Dániel Buga
Dániel Buga
> how that fixes RAM running? It doesn't, but the contributor had run-from-RAM working as is for them. Anyway I don't quite remember at this point what was in my...
I don't think we support this chip currently, that answers the flashing part I believe.
> This might be unique to the [VA416XX](https://www.voragotech.com/products/va41630) chip I am using: The addresses of the NVM and the instruction RAM are identical, and the MCU has a startup process...
> write_8 is used to write the memory while read is used to read back the memory. Is there a specific reason why read is used instead of read_8 None...
> Is it sufficient to just assume that the lowest address is the vector table offset, and then perform the memory region check on that address before calling the ram_flash_start...
> Would adding a entry_point field in the flash loader structure which then gets passed to the new debug sequence be a good first solution? I'm not sure. I think...
Why do you want an `ArmProbe`, why is a `Core` insufficient for this? You may need to import the `MemoryInterface` trait, but it should work I believe.
> Should I introduce a new debug sequence like ram_flash_setup I don't think we should, not for this. For one, the name is super confusing :) Instead, you can disable...
I'm hoping we can get away with minimal changes for the S2 - the TRM seems to mention LCD there as well. Thank you!
Draft for a reason, I want to see where CI breaks.