Bruce Hoult
Bruce Hoult
After running rebase-with-history (which is otherwise *great*) many times, the commit messages get horrible. I think it's better to not modify the messages. Enable this to be opted-out of globally...
> There are 31 registers, x1 to x31, along with x0, which is always 0s. Use the same registers for both integers and floats. (this latter point deviates from RISC-V,...
A little bit whimsical :-) Could add comment that even quite sparse usage will not exhaust it quickly. Calculation (Python): ((2**128 # bytes *8 # bits /6.022e23 # moles *12...
At present 48 bit and 64 bit instructions are encoded in the first 16 bit parcel as: xxxxxxxxxx011111 48 bits xxxxxxxxx0111111 64 bits This is a good scheme. Each extra...
A number of sources say https://riscv.org/angel shoudl work, but it 404s. The readme at https://github.com/riscv/riscv-angel says https://riscv.org/software-tools/riscv-angel/ and that page exists, but the link for "LAUNCH ANGEL" (http://52.32.189.224/angel-simulator/) doesn't work....
We currently support two methods of writing interrupt handlers in C (etc): - assembly-language handler that saves `ra`, `a0`-`a7`, `t0`-`t6` then calls a standard ABI function that can freely use...
It would be useful if the README said how much flash and RAM it uses.
... not even from one instruction to the next one. Any scheme where software reads the cache line size from a CSR or queries to OS for it and then...
We are supporting using the V extension without strip mining in cases where you expect the application vector will fit into one vector register group. It would be good if...
The introduction talks about how DSP is important, and how this extension makes RISC-V faster and more efficient on DSP tasks. Should there not be some words about how P...