Boris Murmann
Boris Murmann
I have managed to get many of the IOPads in the dev branch through the KLayout LVS, but it seems that the IOPadVdd cell has some issues such as some...
I am having some trouble getting the options from the GUI to be correctly reflected in the LVS run. I see that the yml file gets updated when I click...
A series combination of RPPD (as shown below) matches the schematic only with option --no_simplify. But this option won't work for many other parts of a real circuit. Any remedies...
It looks like mimcaps don't get recognized when there is a poly resistor or transistor with the required heat layers underneath. I am am not sure I understand this long...
The pin order of these diodes in spice netlists is alphabetical, and currently gives the pin order cathode, anode. This is incompatible with standard spice, where diodes are instantiated as...
I am not sure of this was brought up here already. The spice pin order between these two stdcell representations do not match up: libs.tech/xschem/sg13g2_stdcells libs.ref/sg13g2_stdcell/spice/sg13g2_stdcell.spice The spice file pins...
1. The gate overlap capacitances seem to be very large. An op analysis for a 5/0.13 NMOS (sg13_lv_nmos) gives cgsol = 3.19575e-15 fF. This corresponds to 0.64 fF/um, about twice...
In SG13G2_os_layout_rules.pdf the layout grid is specified as 5 nm, while in sg13g2.lyt it is set to 1 nm. Is this an intentional scale factor or is there some other...
The simulated gm/gds versus gate bias (for various L) for an lv_nmos looks quite odd for short channels (see plot below). Does the measured data support this? I found only...
Example:  https://colab.research.google.com/drive/1PggoBDvjzV8aN_CluYQCiRV9qptRjlDq#scrollTo=QuGRGGmTCJMi