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Been a couple of weeks now ... any comment @jamesbowman By the way James, excellent Forth, works very well ......
Hi, for no output running python shell I had to comment out: ``` #waitcr() #ser.write(b'\r') #waitcr() ``` .. in reset() function. I am running latest Arch as well. I also...
@RGD2 Thanks for the explanation. I agree sdram is probably not the ideal. I would prefer more fpga ram being freed up, even if it addressed separately. My current requirements...
Got it, thanks. Having 4 threads run as fast as the j1a would be awesome! Having the clock at 160Mhz would help me too, as I would like to clock...
Hi, Yes understand doing it in Forth. But, I want to spit out samples at 48Mhz so have to use verilog .. I would like to know how to format...
Thanks, will look into icebram. I also thought of creating the data as 16bit hex words, swapping the bytes, and adding/replacing the last block of values in nuc.hex (top of...
Any further idea's how I can implement the sine table I need in FPGA? I have no idea how to address it from verilog, even if I put it top...
Never mind. Helps if I read the APIO docs. The command `apio init --scons` creates a SConstruct file which I can modify ... works great.
Any solution to this?
@oskirby Many thanks for the reply. I was asking as I am trying to port your bootloader to the Colorlight i5 board as per: [here](https://github.com/oskirby/tinydfu-bootloader/issues/5) With the resetn GPIO line...