Benoît Denkinger

Hi, I'll will work on the task "Interactive script to select CPU, MEM SIZE, and BUS type" and add the bus option in fusesoc to have something more generic.

Hello, I'm also very interested by converting the regtool hjson format to SystemRDL. I'll support [PeakRDL-opentitan](https://github.com/Risto97/PeakRDL-opentitan) for now. Does the regtool can generate something more than the register files (that's...

> There are a few other generators in the OpenTitan repo that consume these hjson files like [topgen](https://github.com/lowrisc/opentitan/tree/master/util/topgen), [tlgen](https://github.com/lowRISC/opentitan/tree/master/util/tlgen), and [ipgen](https://github.com/lowRISC/opentitan/tree/master/util/ipgen). It's worth checking if those generate what you're asking...

Hello, Thanks for the reply. I'm using SystemRDL to describe full systems (i.e., multiple IP blocks interconnected). In this scenario, SystemRDL is used to define an IP block and signals...