beanspower

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@qarlosalberto Dear expert, The same warning also show when the linter is enabled ![image](https://github.com/TerosTechnology/vscode-terosHDL/assets/46742151/c296de32-f911-4a6c-9e92-aa1cba055890) The linter configuration is shown as below ![image](https://github.com/TerosTechnology/vscode-terosHDL/assets/46742151/ca9ca973-efa9-47ad-a767-2a47e8c3cf72) Besides, if use ` include` all the other...

I use one workaround for this issue. Take the reference from : 1.https://stackoverflow.com/questions/47449489/how-to-include-files-in-icarus-verilog 2.https://github.com/mshr-h/vscode-verilog-hdl-support/issues/51 I add -i and -y arguments in configurations ---- linter settings ----- Linter settings: icarus linter...

@qarlosalberto Hello expert, I try to provide one example code for it. Thanks for your kind help ![image](https://github.com/TerosTechnology/vscode-terosHDL/assets/46742151/440bf0fa-8bde-4809-a0b8-271e919bfab2) [Example.zip](https://github.com/TerosTechnology/vscode-terosHDL/files/12051085/Example.zip)

@qarlosalberto Hello expert, Could you help to check this issue here? Thank for your kind help.

@qarlosalberto Hello Expert , could you help to check it?

@qarlosalberto Hello expert , I share one example as the code in https://github.com/TerosTechnology/vscode-terosHDL/issues/296 Thanks for your kind help. [Example.zip](https://github.com/TerosTechnology/vscode-terosHDL/files/12082019/Example.zip) ![image](https://github.com/TerosTechnology/vscode-terosHDL/assets/46742151/939ea3ad-7a57-4ec1-bb9d-2ad50e68e48f)