awygle
awygle
On Windows, `iter_batched` and `iter_batched_ref` seem to add a significant amount of overhead compared to `iter`. The following benchmark file: ```rust #[macro_use] extern crate criterion; use criterion::{Criterion, black_box}; fn criterion_benchmark(c:...
It would be great to have a linter which reports on things like "you are assigning signals of different widths", "you assign this comb signal in one branch of this...
This PR attempts to address issues #405 , #398 , and #320 by improving error messages for driver-driver conflicts involving Instances. I took my best stab at a better message,...
There is a desire to have a generic stream abstraction in `nmigen.lib` which can be used / presented by the `nmigen-stdio` cores (among others). This issue exists to capture discussion...
`Record.connect` is very rarely useful, but _looks_ broadly useful. It should be deprecated (and ideally replaced with something better).
This RFC is a continuation of #381 . Currently, in order to change the shape of a signal, the following workarounds are needed: * for truncation, use `v[:new_width]` * for...
It would be useful to be able to indicate that a Switch should cover all possible Cases, or at least that the given Cases should not overlap.
The boot code should initialize RDRAM in addition to the RCP. Some partial documentation on how to do this can be found at https://github.com/mikeryan/n64dev/blob/53c2a11f822caa1c96b9bd2eabcb125e5136b37d/docs/n64.lyx. In addition to the RDRAM interface...
As mentioned in a source code TODO, properly doing model equivalence checking on the AsyncFIFO requires using Yosys' multiclock formal support. Currently we check that it meets the FIFOContractSpec in...