aviadb
aviadb
Since last update, the linting is messed up. Trying to lint closed files, non verilog files and many more bugs. which pollute the "problems" tab
A must have feature(s) is the capabilities of verilog-mode to Emacs. auto-inst and auto wire connections
@solomatnikov , did you get past this error? Any updates on this issue? Looks like this is the last blocking bug for enabling proper UVM simulations with Verilator
Hi, looking at the uvm features support testcases here [https://antmicro.github.io/verilator-verification/](https://antmicro.github.io/verilator-verification/) It looks like only 39 tests are failing, meaning that Verilator support for UVM testing should be mature. I am...
Simple vweb setup that loads a template file with an HTML comment. Do you prefer a full working example?
Yes, escaping the variable, i.e. @@numbers solves the problem. However, it would be great to have the flexibility of commenting inside a template file.