Andrew Waterman
Andrew Waterman
Manually merged via https://github.com/riscv/riscv-isa-manual/commit/869dcc608e11f9680e950bcb20a9b8294d2b82bd
The answer follows from the definition of WLRL: https://github.com/riscv/riscv-isa-manual/blob/16f50025273b68de34a4b7c7a397538bd9d508ed/src/priv-csrs.tex#L445
> The spec definition is much looser Yes, the intent was also to permit compression of a sparse set of legal values. If the set of legal values is 0,...
If you’re planning to ship it soon, I strongly advise making it an M-mode-only feature. It’s virtually certain to be at least slightly different than what gets ratified, but if...
Two MRET instructions in a row is going to mess things up for other reasons (namely, it'll change the privilege mode to U, no matter what software intended), so the...
It’s hard to nail this down in the spec, since it requires making microarchitectural assumptions. I’m OK with putting faith in core designers to have good intuition for which clock...
@gfavor was this an omission in the definition of each of the bits, or was leaving them unspecified the intent?
Yeah, I think I agree. In any case, it's still possible to probe whether a specific menvcfg bit is writable, even though menvcfg is not reset. (Not that I'm saying...
We'll discuss it at the next architecture review meeting.
Sorry, I’m not willing to establish the precedent of giving a timeline for this kind of AR. We’ll do our best to be prompt.