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Add draft of RNMI spec
This isn't yet complete, and in particular the inability to directly manipulate the rnmie
bit may be a deficiency. (As it stands, it's impossible to perform the standard pattern of save state; enable interrupts; do something; disable interrupts; restore state. The open question is whether or not this is important to provide for RNMIs, vs. always requiring RNMI handlers to execute with RNMIs masked.)
Does the RNMI handlre have to be able to distinguish between U and VU, S andd VS modes (which would require 3bits of mode), or can the V bit just be retained from the source of the interrupt? This leaves unsaid wheter all the other bit in mstatus woud just be used by nmstatus.
Also, you say "Traps in the RNMI handler can only be resumed if they occur while the handler was servicing an interrupt that occurred outside of machine-mode." which could ve interpreted as "Traps in the RNMI handler can only be resumed if they occur while the handler was servicing *(*an interrupt that occurred outside of machine-mode )." or "Traps in the RNMI handler can only be resumed if *(*they occur while the handler was servicing an interrupt that occurred) outside of machine-mode)."
The former sound more obvious,( and grammatica)l, but you have to think a bit to determine whether the exception source was outside of machine mode, or that the handler is outside of machine mode. It's kind of a long sentence, and breaking it up may make it more clear.
On Mon, Nov 8, 2021 at 6:41 PM Andrew Waterman @.***> wrote:
This isn't yet complete, and in particular the inability to directly manipulate the rnmie bit may be a deficiency. (As it stands, it's impossible to perform the standard pattern of save state; enable interrupts; do something; disable interrupts; restore state. The open question is whether or not this is important to provide for RNMIs, vs. always requiring RNMI handlers to execute with RNMIs masked.)
You can view, comment on, or merge this pull request online at:
https://github.com/riscv/riscv-isa-manual/pull/766 Commit Summary
- Add draft of RNMI spec https://github.com/riscv/riscv-isa-manual/pull/766/commits/5e446b62745d72efb5426fca646edf8d2e86afa8
File Changes
(5 files https://github.com/riscv/riscv-isa-manual/pull/766/files)
- M src/priv-csrs.tex https://github.com/riscv/riscv-isa-manual/pull/766/files#diff-6e0da2cbc53b762355d76c75e9e3a021d7f798cf7a5e4ec3b9e7a1de617702b7 (7)
- M src/priv-instr-table.tex https://github.com/riscv/riscv-isa-manual/pull/766/files#diff-15441bf75a491735e869331867a13ffe93ae620e443e63f2bd19c8dc4215517f (40)
- M src/priv-preface.tex https://github.com/riscv/riscv-isa-manual/pull/766/files#diff-e67a5604593ccbd8fba60fdbd8f2b7f91865efbb952da2b393dce1e0ef914349 (1)
- M src/riscv-privileged.tex https://github.com/riscv/riscv-isa-manual/pull/766/files#diff-14a400c76e7b31182e99e6e05f7214ba6ec893c878e34116fd35e4b53cc5ce03 (1)
- A src/rnmi.tex https://github.com/riscv/riscv-isa-manual/pull/766/files#diff-48be67c1a214d25ebfd406b6e4acfcc5116f3b05c86fb7c2ed13c9d174d21195 (190)
Patch Links:
- https://github.com/riscv/riscv-isa-manual/pull/766.patch
- https://github.com/riscv/riscv-isa-manual/pull/766.diff
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@allenjbaum This spec is indeed missing an mnstatus.MPV
field (it was written not considering the H extension).
It isn't clear to me that it needs it; that was part of the question. RNMI transitions to M-mode, it can see HSTATUS.SPV and night use that. unless mstatus delegates. I'm not clear if that can work or not, as I don't understand the delegation rules for hypervisor mode.
On Mon, Nov 8, 2021 at 10:18 PM Andrew Waterman @.***> wrote:
@allenjbaum https://github.com/allenjbaum This spec is indeed missing an mnstatus.MPV field (it was written not considering the H extension).
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It is needed; using hstatus.SPV doesn't work, either, because the NMI might occur during HS-mode trap entry, before the hypervisor has had a chance to save that field.
Is mnstatus.NMIE a global enable or a local enable for purposes of deciding whether a WFI is allowed to sleep?
It's meant to be analogous to mstatus.MIE (i.e., global).
Manually merged via https://github.com/riscv/riscv-isa-manual/commit/869dcc608e11f9680e950bcb20a9b8294d2b82bd