Arvind Sudarsanam
Arvind Sudarsanam
Signed-off-by: Arvind Sudarsanam
This PR adds third-party (nvptx, amd) AOT support for SYCL offloading in the clang-linker-wrapper tool. Following list of changes are found; 1. Code inside clang-linker-wrapper has been refactored to get...
This PR adds a missing feature in SYCL hierarchical parallelism support. Specifically, this PR adds support for the case when there are functions between parallel_for_work_group and parallel_for_work_item in the call...
### Describe the bug https://github.com/intel/llvm/pull/14262 is the PR where this error is seen. Error report is here: https://github.com/intel/llvm/actions/runs/9687616520/job/26738219382?pr=14262 ` 2024-06-27T04:04:13.7957983Z /__w/llvm/llvm/toolchain/bin//clang++ -Xsycl-target-backend=amdgcn-amd-amdhsa --offload-arch=gfx1031 -fsycl -fsycl-targets=amdgcn-amd-amdhsa /__w/llvm/llvm/llvm/sycl/test-e2e/BFloat16/bfloat16_vec.cpp -fpreview-breaking-changes -o /__w/llvm/llvm/build-e2e/BFloat16/Output/bfloat16_vec.cpp.tmp2.out 2024-06-27T04:04:13.7959989Z...
Please do not review. only testing.
### Bug description I am trying to gather test failures for an upcoming change in this 'draft' PR. https://github.com/intel/llvm/pull/15121 I see that the AMD/HIP tests are not running. Is there...
When using new offload model for SYCL offload, clang-linker-wrapper gathers all bitcode files and uses llvm-link to link them together. This PR has the following changes: 1. Add SPIRV target...
In clang-linker-wrapper, we do not explicitly check if --linker-path is provided. This PR adds a check to capture this. Thanks