Arindam Bose

Thanks for the quick reply. I put an UART bridge as, ``` ("serial_debug", 0, Subsignal("tx", Pins("U18")), Subsignal("rx", Pins("P16")), IOStandard("LVCMOS33") ), ``` and instantiate the UART in the SoC as `self.add_uartbone(name="serial_debug",...

Also, I tried to remove the reset pin of PCIe: `#Subsignal("rst_n", Pins("M17"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),` but still the same issue persists , i.e., The PCIe was not enumerated.

Thanks @enjoy-digital, that was a great help. I had to install the latest OpenOCD to make LiteX-server working for some reason. Anyways, here is the hexdump of all the registers...

Thanks, I tried that. But unfortunately, that wasn't the cause of the problem. The problem lies in the default placement of the Tx/Rx lane pins of the PCIe IP. In...

@enjoy-digital: Unfortunately you can't change that. I mean if you do the design won't synthesize.