appujee

See the comment below ~Currently there are two blockers to CFI proposal~ ~- depends on Zimop~ ~- https://wiki.riscv.org/display/HOME/Specification+Status~ ~- https://docs.google.com/spreadsheets/d/1SwjOz0xJBrbiwggh7MiwfWF5f-0zY9mjXYd51U0MJog/edit~ ~- cfi extension for landing pads~

With https://github.com/llvm/llvm-project/pull/88954/files clang explicitly passes `+unaligned-scalar-mem +unaligned-vector-mem` to the llvm backend.

Will it be a good idea to add repro tests from https://github.com/llvm/llvm-project/issues/88029, https://godbolt.org/z/ETaKqTTPc in CTS?

> What is a success criteria ? Is it about comparing vectorizable (i.e. that will be vectorized if heuristics are disabled) vs AArch64 and X86 ? It is usually a...

> There is no instruction scheduling for RISC-V vectors. > > vsetvls that aren't explicitly from vsetvl/vsetvlmax intrinsics are inserted on demand. All instructions are created with extra operands holding...

> vsetvli intrinsics are allowed to CSE as of last week. ah ok. this should be sufficient. thanks for clarifying.

Try [-mcpu=cortex-a55](https://android.googlesource.com/platform/build/soong/+/master/cc/config/arm64_device.go#61) for ARM For RISC-V `rv64gcv`, please share if you have a cpu flag that gives better vectorization.

nice! is it possible to know how many loops we start with in both the cases? Like do we have something like 'number of loops analyzed'. It could be that...

That's very promising as RISCV is ahead. I've marked the first item as done. Thanks for helping with this.

> > > There is no instruction scheduling for RISC-V vectors. > > vsetvli intrinsics are allowed to CSE as of last week. > As per: https://github.com/llvm/llvm-project/issues/58834 there is still...