vim-verilog-instance

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2

Hi! Is it possible to add an option thus the comments from the original port list are kept? Thanks!

gogulfresh

Support of wire declaration for the instance ports.

6

before (assume that user copied the port declaration to top) input clk, input [2:0] in_a, input [2:0] in_b, output reg [3:0] out_sum module module_name ( input clk, input [2:0] in_a,...

KyleJeong