anonymous

Questions about host memory access

2

Hi, I have a question about [host memory access](https://github.com/Xilinx/Vitis-Tutorials/tree/2022.1/Hardware_Acceleration/Feature_Tutorials/08-using-hostmem). In common where Vitis xdma is sued, the xdma block design module in FPGA hardware is in charge of data transfer...

FPGA performance question

4

Hi, I'm new at FPGA and have an interest in Vitis. First, I encountered performance bottleneck during FPGA write. ``` $ xbutil validate -d b3:00.1 -r 'dma' Starting validation for...

Curiosity of performance between host_memory_bandwidth and host_memory_bandwidth_xrt

2

Hi, I have a question about the performance between [host_memory_bandwidth](https://github.com/Xilinx/Vitis_Accel_Examples/tree/master/performance/host_memory_bandwidth) and [host_memory_bandwidth_xrt](https://github.com/Xilinx/Vitis_Accel_Examples/tree/master/performance/host_memory_bandwidth_xrt). It seems that they have same kernel and similar host code, but the performance results are quite different....

Hi, I am using xdma shell to interact between host and card. Unfortunately, I can not achieve the expected dma performance for write. While read bandwidth almost saturate the PCIe...

[Question] HP-protected Treiber's stack

8

Thank you always, TA. I think it is minor things (maybe my wrong understanding? or maybe ppt error?),  Don't we need to unprotect the cur between if(this->head.load !=cur) and...

QDMA driver and XOCL driver at same time

1

Hi, I have questions about QDMA driver. As far as I understand, this QDMA driver should follow vivado design flow. Then, is it possible to use QDMA driver as vivado...