Andy Ross

FWIW: we clear the timer hardware at OS start, and are always running our own IDT anyway that will detect and report any spurious interrupts. That's not much of a...

Note that this kind of "record used by a thread only when it's pended" thing is something other areas might productively need to (there's something similar for k_poll vs. COHERENCE...

Unfortunately the cAVS/MTL platforms put registers in that low 512M block, so we can't use the region protection bits to deny access. That region is marked rw/uncached. Whether or not...

Just checked: indeed, the core-isa.h files in the sof tree have XCHAL_HAVE_XLT_CACHEATTR==1 for BYT and APL, but all other platforms (AMD/NXP/MediaTek included) are 0. So that's not really much of...

> Can you check anyway, this could be misconfiguration of the cache_attr for the HW FWIW: the cacheattr register actually doesn't exist on platforms with Region Protection Option, the HAL...

Right. The code is aware of the "with translation" distinction (because it has to set up the top three bits differently), but for compatibility we don't try to do any...

Right. Thus "not much of an option". :)

That matches my experience, though I never tried to probe the exact behavior. For sure I've gotten some reasonable-looking exceptions on null pointer dereferences. It makes perfect sense that the...

To be fair, and the Zephyr docs don't make this clear, west is actually a much easier tool for the "multiple gits" problem than git submodule (or Android repo) ever...

Still outside my area of expertise, but this scheme I like much better than N-thousand-line PRs!