hdl

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Generic TDD Engine

2

Replaces the existing axi_tdd with the new version

podgori

Fmc connections and constraints

6

- Added fmc connection files for all carriers - Added an example file for eval board fmc connections - Added the script that generates constraints based on the two types...

AndrDragomir

Tested in simulation

ronagyl

Update the Vivado version to 2021.2 in - library/scripts/adi_ip_xilinx.tcl - projects/scripts/adi_project_xilinx.tcl

IuliaCMoldovan

projects/common: Create templates for all carriers

3

Added system_top.v and system_project.tcl templates for all carriers

laurent-19

Dev cn0501 intel

1

Rebased and updated project

sarpadi

Copy and pasta for the most part from previous pull request, updated with new quartus version and timing fixes. This pull includes the socdk and, hanpilot dev boards. This, again,...

johnathan-convertino-afrl

- This project builds only with this update: https://github.com/analogdevicesinc/hdl/pull/939! - Was not tested on hardware!

FilipG24

Add ad9083_vna

2

AndreiGrozav

In case of using JESD configurations with more than 6 lanes, Master Clock Generation Block(mcgb) must be enabled for both bonding and non-bonding clock cases when using Stratix 10 H-Tile.

FilipG24