getting-started-with-verilog Module Requests

Module Requests

Open aklsh opened this issue 4 years ago • 2 comments

Comment below for module requests. I'll try to push a design ASAP.

Jul 20 '20 16:07 aklsh

Its asking for Declaration of HA and FA modules

Jan 19 '22 15:01 Nischu2291

Its asking for Declaration of HA and FA modules

The makefile is deprecated as writing and maintaining it was difficult. The method to use now is to manually include all necessary files in the compilation instruction. For eg.,

iverilog testbench.v Adders/HA.v clock.v

Alternatively, you can use the `include statements to include all the necessary files in testbench.v so that you can use

iverilog testbench.v

Jan 20 '22 02:01 aklsh

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Module Requests

getting-started-with-verilog
getting-started-with-verilog copied to clipboard