Getting Started with Verilog

This repository contains some verilog modules which are the elementary and fundamental building blocks of a digital circuit. It is best suited for those who are just getting started with Verilog.

Table of Contents

• Modules
  • Flip Flops
  • Adder Circuits
  • Counters
  • Multiplexers and De-Multiplexers
  • Multipliers
  • Miscellaneous
• Usage and Installation
• Contributing
• License

Modules

Flip Flops

• D Flip-Flop

  • without Clear/Reset
  • with Synchronous Clear/Reset
  • with Asynchronous Clear/Reset

• T Flip-Flop

  • without Clear/Reset
  • with Synchronous Clear/Reset
  • with Asynchronous Clear/Reset

• JK Flip-Flop

  • without Clear/Reset
  • with Synchronous Clear/Reset
  • with Asynchronous Clear/Reset

Adder Circuits

• 1 Bit Half Adder
• 1 Bit Full Adder
• N Bit Carry Look Ahead Adder
• N Bit Ripple Carry Adder

Counters

• N Bit Counter (generic)
• N Bit Johnson Counter

Multiplexers and De-Multiplexers

• 2ⁿ to 1 Multiplexer
• 1 to 2ⁿ De-Multiplexer

Multipliers

• (8 Bit) Wallace Tree Multiplier
• (4 Bit) Serial Parallel Multiplier
• (4 Bit) Booth Multiplier

Miscellaneous

• Clock (customisable tick rate)
• Clock Divider (customisable factor)
• D Latch
• Memory
• 32 Bit LFSR - Pseudo Random Number Generator
• Switch Debouncer
• Pattern Detector
• Two's Complementer
• N Bit Shift Register (universal shift register)
• Typical Example of circuit with datapath and control unit
• N-Bit Barrel Shifter
• FIFO

Usage and Installation

1. Clone this repository to local machine - git clone https://github.com/aklsh/getting-started-with-verilog.git.
2. cd into the repository - cd getting-started-with-verilog/
3. Edit the testbench in the file testbench.v by instantiating the module you want to check, and providing the stimulus in the initial block.
4. Run with make.

Contributing

Feel free to submit pull requests with more such modules. Do take a look at the format of an accepted file before contributing.

License

MIT © Akilesh Kannan