Anderson Ignacio

Error when elab with Vivado

9

Hi, I'm trying to build with Vivado 2020.1 and I'm seeing the following error: ```bash ERROR: [VRFC 10-396] cannot assign a string to an unpacked type [/mnt/hgfs/test/projects/demo/tvip-axi/src/tvip_axi_monitor_base.svh:187] WARNING: [VRFC 10-2663]...

Errors on berkeley testfloat-3e

9

Hi pulp-team, I executed the **berkeley testfloat-3e** in the verilator model of **ri5cy** core with _FPU+DIV_SQRT_ and here are the logs of all tests of **unary** and **binary** functions. I...

FW in ESP8266

1

Which version of AT commands firmware of ESP this code support?

Problem with SoftAP + STA mode

1

Hi tuan, I have been trying at least two weeks ago to configure the device with softap+sta mode with your firmware, but always I can't see the ESP in my...

Argument on Xcelium build forces pre-step setup

14

Hi, could you please remove the default argument "-elaborate" on Xcelium/Ius simulator, to use that you need to force work lib creation previously, what doesn't happen at time 0 when...

Problem during 32bit compilation

3

Hi, I'm trying to build the pk/bbl to a 32-bit target but I think that the right argument it's --with-arch=rv32ima instead of --enable-32bit, also the libs like gcc are not...

Added STLV7325 board

3

Hey @alexforencich, I just added support for one more board, can you merge it?

UDP complete waves

10

Hey Alex, tks again for the IPs, bothering you again about usage! do you know how to get some waves of `udp_complete` module or if there's a diagram of how...

AXI interconnect/crossbar hanging while mult. writes

4

Hey @alexforencich, I'm using your _axi_interconnect_ design to build a small SoC and I'm having an issue where a CPU is hanging due to the intcon not being available to...

Added verilog macro to avoid errors on compilation

1

Verilator raises error once it cannot understand bit width in system verilog auto bit definition greater than 32 bits.