agrobman

Verilator - memory usage during compilation

3

I was compiling 8 cores cluster design - the process allocated ~139GB memory. the simulation of the same design allocated ~70MB memory. Is there any way to reduce memory demand...

bscan_tap module - how does it work?

21

Hi Olof, I'm new in FPGAs and wondering how does your bscan_tap module work ? where are the definitions / descriptions of the BSCAN2 modules? How are some internal wires...

Olof, How and from where do you include generated Swerv defines/parameters? How does the FuseSoc configure the Swerv itself ? ( knows to run swerv.config ?)

xrun compilation error

3

when it try to compile standalone RTL as : xrun submodules/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv rtl/verilog/*.sv I'm getting following error: ``` function slave_mask_t invert_slave_mask; | xmvlog: *E,CFBADT (../rtl/verilog/ahb3lite_interconnect.sv,197|40): Declaration in constant function uses unavailable...