Adam Walker

Question about the performance of the Fixed type

13

I'm implementing an FM radio receiver in clash [here](https://github.com/adamwalker/fpga-fm-radio). The [fixed point](https://hackage.haskell.org/package/clash-prelude-1.6.3/docs/Clash-Sized-Fixed.html) data types have been very useful for keeping track of the decimal point and make DSP super nice...

Feature request: register function without an initial value

7

I'm implementing some DSP functionality that makes use of Xilinx's DSP48 blocks, which consist of a multiplier followed by an optional pipeline stage and accumulator. For example, see here: https://github.com/adamwalker/clash-utils/blob/master/src/Clash/DSP/MAC.hs#L58....

Generate Verilator-friendly verilog

5

Clash generates Verilog that Verilator has difficulty optimising. For example, given the module below: ``` module Mod where import Clash.Prelude count :: (HiddenClockReset dom gated sync, Num a) => Signal...

Could not deduce: (n0 + 1) ~ m from the context: 1 <= m

3

The code below: ```Haskell {- OPTIONS_GHC -fplugin GHC.TypeLits.Normalise -} import Clash.Prelude f :: forall n m. m ~ (n + 1) => Vec m Bool -> Bool f = undefined...

Function to replace slice of vector

5

Would it be possible to add a function, replaceVec, similar to "replace" from CLaSH.Sized.Vector which replaces a slice instead of a single element? Perhaps something like: ``` replaceVec :: (KnownNat...

http://www.ee.ic.ac.uk/pcheung/teaching/ee3_DSD/da.pdf

http://www.burtleburtle.net/bob/c/lookup3.c

http://prng.di.unimi.it/