Andrea Bettati

I noticed that the [exception controller](https://github.com/openhwgroup/cv32e40p/blob/master/rtl/riscv_cs_registers.sv#L821) inside the CSR, sets the `mstatus.mpp` to U, when returning from an ISR that was taken and executed in M mode. From my understanding...

Hi to you all, I'm working on a project based on PULPissimo. We use Genus to synthesize the design and had problem with the verison of `riscv-dbg` [used in PULPissim](https://github.com/pulp-platform/pulp_soc/blob/master/ips_list.yml#L118)o...