ZElkacimi
ZElkacimi
CVA6 always send the issue transaction and the commit transaction at the same clk cycle. It's allowed by the cvxif Spec, but if it is hard coded it may cause...
CVA6 always sets the signal result_ready to 1.
CVA6 do not support dualread and dualwrite from a Coprocessor. Also, related to dualwrite: It is mentioned in the cvxif spec, that **we** is 2 bits wide when XLEN =...
If commit_valid is 1 and commit_kill is 0, then the core guarantees that the offloaded instruction (id) is no longer speculative, will not get killed (e.g. due to misspeculation or...
CVXIF feature missing: wait for the result of the instruction that raise the issue resp.exc signal
CPU shall wait for the result of an instruction that raises the issue_resp.exc=1 signal (by the coprocessor), because it can then no longer retire (or commit via the commit interface)...
In the cvxif Spec, we have the following: - The transaction signaled via issue_req and issue_resp is accepted when issue_valid and issue_ready are both 1. - A CPU is allowed...
When executing a simple test offloading a cvxif instruction (example: with core-v-verif, use the following command to execute cvxif_multi.S test; `python3 cva6.py --testlist=../tests/testlist_cvxif.yaml --test cvxif_multi --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=vcs-uvm`),...
With VCS (which is picky regarding LRM SystemVerilog), I get the following compilation error “ Following verilog source has syntax error : Select on function call uvma_rvfi_instr_mon.sv token is ']'...
Hello, I'm facing an issue with the following function: ``` function void uvmt_cva6_base_test_c::phase_ended(uvm_phase phase); super.phase_ended(phase); if (phase.is(uvm_final_phase::get())) begin uvm_config_db#(bit)::set(null, "", "sim_finished", 1); print_banner("test finished"); end endfunction : phase_ended ``` defined...