Yusuf Celik

The Docker version of Supabase that I was running did not have this issue. It wasn't until I tried to push to production that I noticed this error. Anyways, for...

Dear @miek, thanks for responding--appreciate it! From what I can tell, the working example verilog (generated by Luna), is based on acm_serial.py. I cannot find any references in the verilog...

> As well as the `ulpi_clock`, you also need to provide the `usb_clock` signal which is a 120 MHz clock. This is where most of the logic runs and its...

@Logiase, unfortunately I could not. The best that I had going for me, was the incidental enumeration that would occur once in a blue moon (without changing the software). Tried...

The Docker version of Supabase that I was running did not have this issue. It wasn't until I tried to push to production that I noticed this error. Anyways, for...