vim-SystemVerilog

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add UVM support for syntax high light

sqlmap3

There is an syntax of UVM. Can you add it ? ` "------------------------------------------------------------------------------------- " Vim syntax file " Language: Verilog/SystemVerilog HDL + UVM " Author: Amit Sethi, Amal Khailtash, Khalid...

sqlmap3

Is it possible to enhance the indent for "UVM_INFO" like sentences?

2

Hi WeiChung, Thanks for you SystemVerilog plugins, it helps me a lot in implenting verification environment. I am writing to ask for one enhancement of this plugins for uvm_info sentences....

yuhaos