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Branch of the spec repo scoped to discussion of SIMD in WebAssembly

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In attempting to implement [`fmin` and `fmax`](https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#floating-point-min-and-max), I observed that the semantics of these instructions prevents a single instruction lowering on x64. V8 has a 9-instruction lowering for [F32x4Min](https://github.com/v8/v8/blob/19be4913881bb02c5d9b4f1c7547ee2d1273120b/src/compiler/backend/x64/code-generator-x64.cc#L2531-L2548), for...

perf documentation

Now that SIMD proposal has reached Phase 5, there is a question of where new SIMD instructions should go, what is the process to add new SIMD instructions to Wasm....

Opening this issue to gather questions, or concerns if any exist for a [Phase 5](https://github.com/WebAssembly/meetings/blob/main/process/phases.md#5-the-feature-is-standardized-working-group) vote? The requirements for Phase 5 are that the proposal is feature complete, and can...

This issue is meant to track which projects have updated their implementation to match the final proposal and have shipped by default, if applicable. | Project | status | |...

tracking

The LICENSE file basically says to look at the LICENSE in each subdirectory, but the proposals directory doesn't include one, nor does proposals/simd. I want to steal a lot of...

Currently the intrinsic header uses a different naming convention than the underlying SIMD instructions. The intrinsic name can be determined from the instruction name by prepending `wasm_`, turning the `.`...

toolchain

# Introduction This proposal introduces an extended horizontal multiply and add instruction that is used extensively in colorspace conversion and in the implementation of encoders and decoder for video processing....

post SIMD MVP

Introduction ========= Pairwise addition (AKA horizontal addition) is a SIMD operation that computed sums within adjacent pairs of lanes in the concatenation of two SIMD registers. Floating-point pairwise addition is...

post SIMD MVP

# Introduction Most modern processors support Fused Multiply-Add (FMA) family instructions. These instructions compute multiplication and addition of floating-point numbers **without** intermediate rounding. Elimination of intermediate rounding improves accuracy in...

post SIMD MVP

(Yeah, I know we're done but I figured it was more natural to file the issue here than in relaxed-simd. Looking for feedback.) Generally JS does not have a representation...