OpenRAM

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ImportError: Missing 'lef_rom_interconnect' in stable version's OpenRAM tech module

4

**Describe the bug** When compiling SRAM using the command line, the following error occurs: from openram.tech import drc, layer, parameter, lef_rom_interconnect ImportError: cannot import name 'lef_rom_interconnect' from 'openram.tech' **Version** OpenRAM...

OsFlora

Sense amp enable timing error when generating 1 Kb (1024 bits) SRAM — requires manual delay chain adjustment

1

**When trying to generate a 1 Kb (1024 bits / 1 KB) SRAM, OpenRAM fails due to a “Sense amp enable timing error.” I tried manually increasing the delay chain...

cyberxcodes

Spare columns are considered as extra data bits, thus extra pins are added. However, the data bus size on the liberty file only accounted for the real data bits. This...

martialonso

Please consider switching from `volare` to `ciel`

2

As support for Volare will not happen in the future, a switch to Ciel (the successor) should be considered.

hpretl