Topi-ab
Topi-ab
My colleagues don't like my habit of always finding corner cases ;) I would expect them to behave identically. And both should keep waiting for cover until cycle 12. There...
Valid use case: A cover to check that the output port can transition. This would be to find forgotten assignments.
I understand. Do you agree that both a and b should give the same cover result?
I passed test.vhdl through yosys: ``` yosys -m ghdl ghdl --std=08 test.vhdl -e test opt write_verilog test.vo ``` For me it looks like the first cover is trying to cover...
As a sidenote, attributes `anyconst` and `allconst` can mimc `forall` in some cases (in sby formal verification flow). `assert forall i in {0 to 1}: always ((a=i -> eventually! b=i));`...
This would be really useful for generalizing checkers.
Sorry, I misread the version (v4.1.0-138...). Correct one seems to be 5.0.0-dev And it synthesizes the example. I've been using stable() criteria for a long time (which seems to be...
Or could it be "llvm 14.0.0 code generator" vs "static elaboration, mcode JIT code generator"?
My bad ! Changing the ghdl invocation to: `ghdl --synth --std=08 ghdl_bug_2025-03-05.vhdl -e ghdl_bug_2025_03_05` solved the problem. I don't need to simulate the code, only run in formal (i.e. synthesize).
> Your GHDL is from 28.07.2024 ([a00b783](https://github.com/ghdl/ghdl/commit/a00b7833f1e07c12013346a2f703810fb6c87f59)). It's a v5.0.0-dev (138 commits after v4.1.0 was release). You could upgrade to v5.0.1 or compile from sources to get v6.0.0-dev. This is...