TimRudy

Hi James, thanks! Great to see your CPU project. That is going to be fun, and it's just what these parts are for :-) I will create a tristate branch...

It's expected. The ice-chips code may have to consider using an ifdef so the code is general, as for example: https://www.reddit.com/r/yosys/comments/6e9qka/either_parsing_or_ignoring_testbench_code On Mon, Jan 25, 2021 at 7:56 AM James...

The syntax error is on track to go away in the future! Pull request is being considered: https://github.com/YosysHQ/yosys/pull/2566

James, I'm pretty fired-up. I just realized due to looking things up this evening, in the Verilog manual the LRM, that the #(DELAY_RISE, DELAY_FALL) can be extended because there's a...

Syntax error will be gone now if you get the latest Yosys.

Thank you! Tri-state is a special case but these are on my TO-DO list

Awesome, sorry I did not get the notification and see this note. The 4040 and the 40103 are pretty straightforward, we should talk out-of-band and you can get going on...

74x4040 binary counter: easy implementation like existing counter, does anyone need it? 74x40103 down counter: easy implementation like existing counter, does anyone need it? 74x4046 PLL and VCO: no-no-no-no, I...

For arithmetic, compare, min and max, I see what you're saying and this collection [github.com/TimRudy/ice-chips-verilog](https://github.com/TimRudy/ice-chips-verilog/blob/master/device-index.md) was created to make general code available and it is tested/trusted. Each block can be...

It will be up to the user of the Verilog code block to say whether the block is doing signed or unsigned (*let's start with an adder/subtractor), as numbers are...