Tang Haojin

抱歉，想再问一下，如果要把textcite里的英文括号也改为中文括号，需要怎么办呢？

谢谢

The vector extension is still work-in-progress. It may be more stable after Apr. 30.

You may see here: https://github.com/OpenXiangShan/XiangShan/blob/master/build.sc#L159 It is true that fudian's build.sc is still using chisel 3.6, but the codes of fudian modules are already compatible with chisel 5/6, so we...

> OK this is certainly a bug. Like declaring register or memory inside when block. In the boring utils case, I personally think it should be forbidden. I agree that...

I tried Visual Studio 2022 17.8.1 for both commit `5838a9e`, which is the last version passing windows build, and the next commit `0d48f71`. `5838a9e` can pass all tests, while `0d48f71`...

I installed vs2022 build tools through [this link](https://download.visualstudio.microsoft.com/download/pr/1ddfd51d-41a3-4a5f-bb23-a614eadbe85a/0424cf7a010588b8dd9a467c89c57045a24c0507c5c6b6ffc88cead508b5f972/vs_BuildTools.exe), which lies in [Visual Studio 2022 Release History](https://learn.microsoft.com/en-us/visualstudio/releases/2022/release-history#fixed-version-bootstrappers).

I found that simply change `unsigned` to `size_t` can unbreak this issue on my local machine: ``` diff diff --git a/lib/Dialect/FIRRTL/Transforms/Dedup.cpp b/lib/Dialect/FIRRTL/Transforms/Dedup.cpp index dc244a26d..1750509bb 100644 --- a/lib/Dialect/FIRRTL/Transforms/Dedup.cpp +++ b/lib/Dialect/FIRRTL/Transforms/Dedup.cpp @@...

Thank you for your reply. I know little about the implementation detail of circt, but I found that the `assert` in Verilog here is a little similar to what we...

Yes. Hartid is hard-encoded in PerfCounter, PerfRolling, ChiselDB, ConstantIn, tp prefetcher, etc., which should be avoided. This PR use dynamic hartid instead, and the verilog-generation time of dual-core is almost...