[BUG] The swmod signal ignores swwe/swwel

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Describe the bug The swmod signal asserts when swwe/swwel are not asserted. The specification states that swmod asserts when the field is "modified by software". When the swwe/swwel inputs are not asserted the field is not modified and the write access is ignored so I expected SWMOD to not assert.

Here is an example;

    reg {
        field { hw = r; sw = rw; } size[4] = 12;
        field { counter; hw = r; sw = rw; } addr[15];
        field { hw = r; sw = rw; } read_only = 1;
    } CONFIG;

    reg {
        field { swmod; swacc; swwel; hw = rw; sw = rw; } access;
    } ACCESS;
    // NOTE: swmod will ignore the state of read_only. External
    // logic needs to gate RAM writes based on read_only AND swmod.
    CONFIG.addr->incr = ACCESS.access->swacc;   // Auto increment address on access
    ACCESS.access->swwel = CONFIG.read_only;    // Enable write only when read_only == 0

The generated SystemVerilog code correctly gates software writes.

if(decoded_reg_strb.ACCESS && decoded_req_is_wr && !(field_storage.CONFIG.read_only.value)) begin

The SWMOD output however ignores the write enable signal, which feels like a bug.

assign hwif_out.ACCESS.access.swmod = decoded_reg_strb.ACCESS && decoded_req_is_wr;

Expected behavior What I expected in this scenario is SWMOD would only assert when the register field is modified.