Josep Sans

``` verilog module test; logic [7:0] k; logic clk_i; logic rst_ni; always_ff @(posedge clk_i or negedge rst_ni) begin if(~rst_ni) begin k

``` module test; struct { logic x; logic z; } k [1:0]; logic clk_i; logic rst_ni; logic a, b, c, d; always_ff @(posedge clk_i or negedge rst_ni) begin if (~rst_ni)...

slang: Add AST Matchers

1

Add the capability to match the AST Nodes ala clang matchers. Combining different Matchers and using the MatchFinder, the user will be able to match specific nodes in the AST...