kronos
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SonalPinto
Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations
Hi there! I found a bug in Kronos that in some cases ignores the second consecutive write to a given register in case of a WAW dependency. A problematic example...
Hello, we have found a security vulnerability in the Kronos CPU where an instruction sometimes reads from the previous' instruction's input register. For example, a 'jalr' instruction may read from...
To exploit this vulnerability, the attacker consistently set the "data_ack_i" signal to 1. This behavior is permissible according to the Wishbone Interface Specification, which Kronos core is designed to follow....
To exploit this vulnerability, the attacker consistently set the "data_ack_i" signal to 1. This behavior is permissible according to the Wishbone Interface Specification, which Kronos core is designed to follow....
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Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations