Bug report: stale register value in case of double write

[flaviens]

Hi there!

I found a bug in Kronos that in some cases ignores the second consecutive write to a given register in case of a WAW dependency. A problematic example is the following:

• The first instruction writes to, say, ra, for example add ra, t0, zero.
• The second instruction writes to ra again and has no dependency with the previous instruction, for example add ra, t1, zero, where we assume t0 != t1.
• The third instruction depends on ra, say add t2, ra, zero. Then, given the behavior of the current HCU, will not stall because it sees a write-back to ra. However, this is the write-back from the first instruction and forwards stale data. The final state of this scenario is t2=t0 instead of the expected t2=t1.

Kind regards, Flavien