Rubiczhang

同学你好，关于lab3的ClockSwapper我有一些疑问： ```rust fn pop(&mut self) -> Option { let len = self.queue.len()-1; let mut index:usize = 0; let mut isfound:bool = false; unsafe{ loop{ for i in 0..(len+1){ //为什么让pe =...

Hello everyone, I'm a Newbie who study yaml and cerberus first time. I found that in riscv-config/riscv_config/schemas/schema_isa.yaml:line181. The key 'max' has a value '[56]'. ```yaml physical_addr_sz: type: integer max: [56]...

Hello Zhang Wenting: I have run rv64um isatest on your multiplier, but the result is wrong. I have noticed that when you calculate middle result (mac_a * mac_b), you simply...

Internal Error instead of normal error for same specparam in different generate-for loop

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Hello, I get Internal Error when compile such verilog code: ```verilog genvar i; generate //cvt kbd_code_buf, and put result into kbd_segcode for(i = 0; i < 2; i++) begin: gen_cvt...