Fix failing simulation in Vivado

[AngeloJacobo]

Good day,

(creating another PR as my previous one include the whole master branch)

Simulation is failing in Vivado simulation:

Looking on the testbench, it seems that the ch_enc_d is being compared to dec_q but the ch_enc_d is 1 cycle earlier relative to dec_q (as shown on the simulation below), causing all comparisons to fail in domino effect:

The simplest fix I saw is to change the edge of the testbench clock from posedge to negedge. And its passing now:

As an extra, I just added a slight fix to the syntax error in the file altecc_enc.v just to make the tool happy.

Thank you very much!

Kind regards, Angelo

[rherveille]

The silly 'i' typo I incorporated and pushed. However the simulations pass here without your changes. What simulator are you using? How do you run the simulator; i.e. using what command

[AngeloJacobo]

Hi,

I am using the Xilinx Vivado simulator (Vivado 2022.1 specifically). I am not sure of the commands as I'm using the GUI. Importing all files from this repository, setting the testbench_top as the top-level simulation file, then just running the simulation will start and run the simulation.