Risto Pejašinović

[https://github.com/Risto97/pygears_issues/blob/master/data_dly/run_test.py](https://github.com/Risto97/pygears_issues/blob/master/data_dly/run_test.py) Verilator fails to compile data_dly gear because of missing dreg.sv. I see 3 ways for resolving this. -Append dreg verilog module in data_dly.sv file (simplest). -Generate dreg gear modules...

This test is failing: [https://github.com/Risto97/pygears_issues/blob/master/timeout_test/run_sim.py](https://github.com/Risto97/pygears_issues/blob/master/timeout_test/run_sim.py)

Assertion signal stable value

11

Hello, I am trying to integrate your project in my Systemc-UVM testbench. I have run into few things that are missing for me, or I dont know how to write...

I am not sure if I understood the documentation correctly, but it seems like the WFI (wait for interrupt) instruction is not implemented? Or rather just implemented as NOP These...

Verilator support

3

I done a series of pull requests in Verilator in order to support the code regblock is generating. In the next release 5.12 I believe most of the things will...

[BUG] Verilog preprocessor, `ifdef around `include statement

3

- [x] I have reviewed this project's [contribution guidelines](https://github.com/SystemRDL/systemrdl-compiler/blob/main/CONTRIBUTING.md) **Describe the bug** In the following code: ``` `ifdef SOME_MACRO `include "inc.rdl" `endif addrmap test { reg { field { hw...