language-verilog
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Verilog language support in Atom
Embedded [tree-sitter-verilog](https://github.com/tree-sitter/tree-sitter-verilog) parser into the package.
Fixed casex/z keyword Added enhanced literal number detection from sublime Added module header punctuation scope to prevent last line in header being recognized as module instantiation
When the closing paren is on its own line, the last port of a module declaration is highlighted in red: ``` verilog module Id( input in, output out ); assign...
I am editing verilog file which is 118514 lines long, but verilog syntax does not work for such long files. It works well for shorter files. How can I fix...
It seems that a mistake has been made in keyword. There is a 'longing' keyword and I suppose it should be 'longint'.
First thank you for developing this package. Here is a small bug.  "unique case" is not a module instance. These 2 words and the first semicolon are not highlighted...
1. fix "longing" to "longint" 2. "unique case" & "priority case" will not be treated as instance now. (refer my issue for more details My source file is downloaded from...
In verilog we don't need matching quotes. They are used as singles only.
When pressing "ctrl-/" it inserted "/\* _/" instead of "//". For example: /_this is a comment*/ But I expected: // this is a comment
generate
Salam (Hello) tank you for your code; can you add diffrent color for parameter variable (better visual view)? can you add diffrent color for instance name for module (//)? can...