Robert Schilling

Results 19 issues of Robert Schilling

I have the following empty entity: ``` ruby class Project < Grape::Entity end ``` Although the entity is empty the JSON response contains a field `permission`: ``` json { "permissions":...

bug?

By using top-level straps for the PMP reset configuration its easier to implement different reset configurations if there are multiple Ibex cores in the system.

Component:RTL

I'm working towards adding support for multiple CPUs within the OpenTitan complex. With this change, `topgen` supports MMIO regions in multiple address spaces. It requires associating each memory with an...

Component:Tooling
Component:Darjeeling

Previously, clearing the DONE or ERROR interrupt before clearing STATUS.done would raise the same interrupt a second time, which could bring FW out of sync. With this change, the DONE...

Component:Darjeeling
IP:dma

The memory interrupt allowed the system to configure a soft and hard memory limit address. When reaching one of those limits during a DMA transfer, the DMA would fire the...

Component:Darjeeling
IP:dma

Previously, the error code is written when entering the error state AND while being in there. Since the error code value is only availble in the transition into the error...

Component:Darjeeling
IP:dma

This PR connects the SPI device to the DMA to be able to be used with the DMA hardware handshake mode. Doing so, this PR adds the following changes: *...

Component:Darjeeling
IP:dma

This PR adds a new STATUS.chunk_done bit to the status register to determine the cause when the DMA stopped an operation. In multi-chunk mem2mem transfers, where each chunk is transferred...

Component:Darjeeling
IP:dma

This PR syncs the DMA DIF from `integrated_dev` to `master`. This PR depends on https://github.com/lowRISC/opentitan/pull/24434

Component:MultiTop
IP:dma