Gang Yuan

Sorry for late response, hi, @anonymous1782, I run the sweep test and get following figure. Sure, you are right that the Y axis is FPGA throughput and the unit is...

Sorry for late response. Generally, the following two license keys are needed: xxv_eth_mac_pcs x_eth_mac Or refer to following link: https://www.xilinx.com/products/intellectual-property/ef-di-25gemac/ef-di-25gemac-order.html If the evaluation licenses are not working, please check the...

Hi, @arishsatheesan, when you apply for the evaluation license from the Xilinx licensing site, you should add both following items, like the snapshot below: After importing the generate license file,...

I've tried the license generation flow as mentioned above using a fresh new machine, and the flow can pass. When the generated license is imported with Vivado license manager, whether...

Hi, @xooxit , sorry, I cannot re-produce the errors with same configuration. Below is my relevant log segment. Would you please help to confirm whether the _Makefile_ and _krnl_aes_test.xdc_ files...

Sorry for late response. Hi, @zhuofanzhang, are you using the 10Gbps or 25Gbps lane rate? If it is the latter case (25Gbps), first you will need a QSFP28 (25G) loopback...

Hi, @zhuofanzhang, are you connecting two QSFP28 ports in a card (one as TX and another as RX), or connecting two cards? I will try to reproduce your scenario to...

Hi, @zhuofanzhang, the bit error might be brought by a few factors, could you please use a loopback module first to exclude the logic design issues? For fiber case, you...

Hi, @eerobert, are you using all the default configuration with "make all LANE=4" command to build? Could you provide the platform and Vitis version, as well as the GitHub repo...

Hi, @eerobert, I tried and re-product the issue, I will dig into this and please use 2022.2 version temporarily. Thanks.