Rajnesh

Running bare-metal firmware on latest CVA5 core

1

Hi everyone, I have added the latest CVA5 core (found here: https://github.com/openhwgroup/cva5) to `pythondata-cpu-cva5` (replacing the original core contents Litex has in `pythondata-cpu-cva5/pythondata-cpu-cva5/system_verilog` with what's currently on the main branch...

Writing drivers for Timer peripheral

1

Hello, I have added a TIMER to my CPU that is being simulated through LiteX. The details of the TIMER can be found [here](https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/#counter-timer). It is a CSR memory-mapped timer....

How to contribute to LiteX Wiki?

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Hello, I want to know how I can contribute to LiteX Wiki so that I may add documentation where necessary to support people using the tool, and I would like...

Disabling interrupts in bios for serial boot, re-enabling when files are uploaded completely.

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Does anyone have any thoughts on the value of creating a PR that disables interrupts in the bios before it begins serial booting and downloading files via serial? I am...