Simon Pilgrim

No, in this case we need to be told whatever the opcode is, not match for an explicit opcode

@mshockwave Any suggestions please?

https://godbolt.org/z/W1r1c4fzY

I expect all of this to be handled as DAG combines inside X86ISelLowering.cpp

I suggest you start with the SRA(X,UMIN(Y,BW-1)) case in combineShiftRightArithmetic You should be able to use supportedVectorVarShift to detect when the target supports replacing the ISD::SRA node with X86ISD::VSRAV

The code below that early-out is for a single fold (see the description comment) - just above it is the combineShiftToPMULH fold - you can put your code after combineShiftToPMULH.

The order looks to just be the difference between Intel and AT&T ASM ayntax

I suggest you just focus on the SRA case first

That SRA code looks fine - I'd like to see it in a PR, and then there is the question of adding test coverage....

> @RKSimon, Do tests need to be changed in combine-sra.ll? Yes