Fan Jiang

Bumping this issue. SPI sharing is a **very** common use case and this can be easily supported by introducing a `SpiClock` struct that has `From` and let the `SpiBus::Config` struct...

> * Would hardware atomics work correctly, if the programmer is ensuring that the relevant PSRAM memory region is accessed only by **one** of the two CPUs? I think the...

> No, see RP2040 Beaten me in 5 secs lol > Ah so you mean for rp2040 they use a spinlock+disable-all-interrupts software impl? If yes, then this only reinforces my...

A gentle ping here @ivmarkov @MabezDev On the IDF part, I believe IDF already provides some kind of critical section: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/system/freertos_idf.html#api-changes which can be used directly

Wonder what's the status on this? Just checking in :)

Hey guys, I am the reporter of the original problem in ESP-IDF FreeRTOS. Yes, this is a silent data corruption and the current ESP-IDF's interrupt vector assembly file has a...

> > my thinking was that at least for the things indirectly allocated from the driver via malloc we currently allocate from internal-ram - we don't have control over that...

Just stumbled upon the same problem on Arch Linux. A simple patch ```c++ DearPyGui/src/platform/Linux/mvLinuxViewport.cpp ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── ────────────────────┐ namespace Marvel { │ ────────────────────┘ 132 // Setup style ImGui::StyleColorsDark(); auto& style = ImGui::GetStyle();...

GPIO matrix will be a great addition, many great hacks around RMT/I2S etc etc can be enabled by the GPIO matrix.

Another use case is I2C/SPI on multiple pins. This significantly improves board routing and allows much better signal integrity by avoiding long buses.